The present invention relates to a technique to optimize a connection configuration of a plurality of memory devices and a data processing device for controlling the same on a wiring substrate, and an output phase relationship between a clock signal and a command and address signal which the data processing device supplies to the memory devices. For example, the present invention relates to a technique effectively applied to a semiconductor device in the form of a mother board having a DDR (Double Data Rate) 2-SDRAM (Synchronous Dynamic Random Access Memory) compliant with JEDEC STANDARD No. 79-2D and a memory controller mounted therein.
Patent Document 1 (Japanese patent laid-open No. 2007-213375), which is the previous application by the present applicant, discloses a semiconductor device in the form of a mother board, wherein a memory controller is on-chip mounted along both side edges of a corner portion of a data processing device in the form of an SOC, and a memory device is arranged opposite to the corresponding both side edges, respectively. This specification discloses a configuration in which two DDR2-SDRAMs are arranged as the memory devices and the data processing device simultaneously accesses these memory devices. In particular, while a command and address signal is supplied in parallel from the data processing device to the memory devices via a common substrate wiring, a clock signal is separately supplied to the memory devices via separate clock wirings.